IAR Embedded Workbench for RISC-V

• Scalar Cryptography (Zkn, Zks) Instruction Set Extensions
  The Zkn and Zks RISC-V extensions implement Scalar Cryptography instructions aimed at accelerating the NIST and ShangMi cryptographic standards, respectively. 
• Code Size Reduction (Zcb, Zcmp) Instruction Set Extensions
  The Zcb standard extension provides compressed variants of a number of existing extensions. The Zcmp extension is a set of instructions (including push/pop) that can be executed as a series of existing 32-bit RISC-V instructions.
• Improved code generation for the Bitmanip extensions
• Optimized ceil, floor, and round libraries for soft-float and Zfinx
• Support for misaligned data access
• New compiler GCC extensions 
• IDE Build Actions improvements
  Build actions replace the previous pre- and post-build actions with a more intuitive mechanism, to which multiple actions can be executed before compilation and before/after linking.
• Breakpoints
  Breakpoints can now be set during application execution, even when there is no hardware support for it.
• New devices

Zfinx and Zdinx standard RISC-V extensions

• Support for standard extensions for Floating-Point in Integer Registers.

CMO standard RISC-V extensions

• Support for the Cache Management Operations (CMO) extensions Zicbom, Zicboz, and Zicbop.

Auto compressing Assembler

• When support for the C extension is enabled, the assembler automatically converts normal instructions to compressed instructions.

Optimized ceil, floor, and rounding library functions

Improvements for the Andes performance extension on RV64

Improved code generation for the Bitmanip extensions

Asymmetric multicore debugging improvements

• It is now possible to perform multi-architecture AMP debugging using two IAR Embedded Workbench instances installed in separate directories. The IAR Embedded Workbench instances no longer have to be installed in the same directory.

Support for Nexus serial trace

• With an I-jet Trace probe, it is now possible to enable serial trace (serial pin).

New devices

• Sifive
  E6-A
• Nuclei
  NA900
• Frontgrade Gaisler
  GP32L-SC
  GP64L-SC
  MC32L-SC
  MC64-SC

• Andes CoDense extensions
  Andes V5 architecture code density enhancement, to reduce program code size
• P extension support
  Standard Extension for Packed-SIMD Instructions, updated to 0.9.11
• Debugger enhancements
  GDB server improvements – more debug server variants supported
  SMP and AMP multicore debugging improvements
• Editor enhancements
  Window color themes – dark mode improvements
• Visual Studio Code extensions
  The IAR Build and IAR C-SPY Debug extensions available on Microsoft Marketplace enable you to work in Visual Studio Code (with IAR Embedded Workbench installed) to: 
  - Build IAR Embedded Workbench projects
  - Run the C-STAT static analysis tool
  - Debug applications using the same range of hardware/debug probes as in IAR Embedded Workbench
• New devices

64-bit RISC-V core support

• Support for RV64 RISC-V cores and the RV64I base instruction set
• Support for RV64 devices from Andes, Codasip, Microchip, Nuclei and SiFive

Library support for the C++17 language standard

• The toolset now includes a new C++ library that supports C++17 library features.

Debug enhancements

• RV64 core debug support
• SMP multicore debug support for I-jet

Editor enhancements

• Window color themes - dark mode
• Gray out inactive code